1. Field of the Invention
This invention relates to j-MOS transistors, which combine the features of both a JFET and a MOSFET, and in particular to an improved j-MOS transistor which operates at higher current densities.
2. Description of Prior Art
FIG. 1 shows a typical prior art j-MOS transistor as described in the article, "j-MOS: A Versatile Power Field-Effect Transistor", by B. A. MacIver et al., IEEE Elec. Dev. Ltrs., Vol. EDL-5, No. 5, May 1984, herein incorporated by reference. The j-MOS transistor in FIG. 1 includes substrate 10, insulation layer 15 formed over substrate 10, N+ source region 20, N+ drain region 21, N- channel 22, gate 25 formed over and insulated from channel 22 by gate oxide layer 24, and P+ region 23 formed in channel 22 and in electrical contact with gate 25. Metal contacts 26, 27, and 28 provide electrical contact to source region 20, gate 25, drain region 21, respectively. When gate 25 is at the source voltage (i.e., V.sub.GS =0), current flows between source region 20 and drain region 21 through channel 22 as if the transistor was a JFET. When the gate voltage is positive with respect to the source voltage, but less than about 0.6 volts, an increased current flows between source region 20 and drain region 21 due to an accumulation of electrons in channel 22. The device is now behaving like a combined JFET and MOSFET. When V.sub.GS is greater than 0.6 volts, the P-N junction formed by P+ region 23 and N- channel 22 becomes forward biased, and the conductivity of the channel region is modulated by the injection of holes into the channel, thus further reducing the resistance of the channel. If P+ region 23 contained an N+ region electrically coupled to gate 25, and P+ region 23 was otherwise insulated from gate 25, P+ region 23 would not become forward biased, and the conductivity of the channel would be modulated due to an accumulation of electrons in N-channel 22.
When gate 25 is at a negative voltage with respect to source region 20 (i.e., V.sub.GS =-V), the device behaves like a JFET with a reverse biased gate, and the electric field created between gate 25 and channel 22 decreases the number of free electrons in channel 22, thus increasing the ohmic resistance of channel 22. P+ region 23 acts to sink holes generated in channel region 22, thus keeping the device turned off. In an alternative embodiment, substrate 10 and insulation layer 15 may be replaced by an insulating substrate of sapphire.
A higher current variation of the j-MOS transistor has been proposed and investigated. This variation, shown in FIG. 2, uses N+ substrate 30 as a drain to form a vertical j-MOS transistor. In FIG. 2, N+ source regions 32, 33 are insulated from N+ substrate 30 by insulating regions 34, 35, respectively. N- channel 36 is formed between source regions 32, 33 and contacts substrate 30 via an opening between insulating regions 34, 35. P+ regions 37, 38 are formed in channel 36 and are in electrical contact with gate 39, which is formed over channel 36. Gate 39 is insulated from channel 36 via insulation layer 40 and is insulated from source metal contact 41 via insulation layer 42. This device performs similarly to that shown in FIG. 1, except that current flows from the source from both sides of gate 39, thus providing a greater cross-sectional area through which current can flow. Another difference is that current flows vertically through substrate 30. The j-MOS of FIG. 2 is difficult to fabricate due to the difficulty of forming single crystal silicon over SiO.sub.2 regions 34, 35.
It is seen that prior art j-MOS devices require some lateral current flow through the channel. It is well-known that higher current densities (Amperes.multidot.cm.sup.2) are obtained by reducing channel width, or otherwise reducing channel resistance, and that a higher current handling capability is obtained by increasing channel cross-sectional area. One limiting factor in achieving higher current handling capability is that the channel must be thin enough to be adequately depleted upon application of a preselected voltage to the gate. Vertical j-MOS transistors, such as that shown in FIG. 2, enable higher current densities, but channel thickness still remains a limiting factor to higher current handling capabilities.